View HM62W1400HSERIES_318954.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM62W1400H Series
4194304-word x 1-bit High Speed CMOS Static RAM
ADE-203-773 (Z) Preliminary Rev. 0.0 Apr. 28, 1997 Description
The HM62W1400H is an asyncronous high speed static RAM organized as 4-Mword x 1-bit. It has realized high speed access time (10/12/15 ns) with employing 0.35 m CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W1400H is packaged in 400-mil 32-pin SOJ for high density surface mounting.
Features
* Single supply : 3.3 V 0.3 V * Access time 10 ns/12 ns/15 ns (max) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible All inputs and outputs * 400-mil 32-pin SOJ package * Center VCC and VSS type pinout
Ordering Information
Type No. HM62W1400HJP-10 HM62W1400HJP-12 HM62W1400HJP-15 HM62W1400HLJP-10 HM62W1400HLJP-12 HM62W1400HLJP-15 Access time 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns Package 400-mil 32-pin plastic SOJ (CP-32DB)
Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice.
HM62W1400H Series
Pin Arrangement
HM62W1400HJP/HLJP Series
A0 A1 A2 A3 A4 A5 CS VCC VSS Din WE A6 A7 A8 A9 A10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A21 A20 A19 A18 A17 A16 OE VSS VCC Dout A15 A14 A13 A12 A11 NC
Pin Description
Pin name A0 to A21 Din Dout CS OE WE VCC VSS NC Function Address input Data input Data output Chip select Output enable Write enable Power supply Ground No connection
2
HM62W1400H Series
Block Diagram
(LSB) A0 A1 A2 A3 A4 A5 A6 A7 (MSB) Din
VCC Row decoder Memory matrix 256 rows x 16384 columns x 1 bit (4,194,304 bits) VSS
CS Column I/O Dout Column decoder CS
CS WE OE
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 (LSB) (MSB)
CS
Function Table
CS H L L L L Note: OE x H L H L x: H or L WE x H H L L Mode Standby Output disable Read Write Write VCC current I SB , I SB1 I CC I CC I CC I CC I/O High-Z High-Z Dout Din Din Ref. cycle -- -- Read cycle (1) to (3) Write cycle (1) Write cycle (2)
3
HM62W1400H Series
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +4.6 -0.5* to V CC+0.5 1.0 0 to +70 -55 to +125 -10 to +85
1
Unit V V W C C C
Notes: 1. VT min = -2.5 V for pulse width (under shoot) 10 ns
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC* VSS * Input voltage VIH VIL
2 3
Min 3.0 0 2.2 -0.3*
1
Typ 3.3 0 -- --
Max 3.6 0 VCC + 0.3 0.8
Unit V V V V
Notes: 1. VIL min = -2.0 V for pulse width (under shoot) 10 ns 2. The supply voltage with all VCC pins must be on the same level. 3. The supply voltage with all VSS pins must be on the same level.
4
HM62W1400H Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0V)
Parameter Input leakage current Output leakage current Operation power supply current Symbol Min IILII IILO I 10 ns cycle I CC 12 ns cycle I CC 15 ns cycle I CC Standby power supply current 10 ns cycle I SB 12 ns cycle I SB 15 ns cycle I SB I SB1 -- -- -- -- -- -- -- -- -- Typ*1 -- -- -- -- -- -- -- -- -- Max 2 2 240 200 190 100 100 100 10 mA VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V mA CS = VIH, Other inputs = VIH/V IL Unit A A mA Test conditions Vin = VSS to V CC Vin = VSS to V CC CS = VIL, lout = 0 mA Other inputs = VIH/V IL
--* 2 Output voltage VOL VOH -- 2.4
--* 2 -- --
0.5*2 0.4 -- V V I OL = 8 mA I OH = -4 mA
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25C and not guaranteed. 2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = 25C, f = 1.0 MHz)
Parameter Input capacitance*
1 1
Symbol Cin CI/O
Min -- --
Typ -- --
Max 6 8
Unit pF pF
Test conditions Vin = 0 V VI/O = 0 V
Input/output capacitance* Note:
1. This parameter is sampled and not 100% tested.
5
HM62W1400H Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: 3.0 V/0.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5V Output load: See figures (Including scope and jig)
3.3 V
319 Dout Zo=50 RL=50 30 pF Dout 353 5 pF
1.5 V Output load (A)
Output load (B) (for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW)
Read Cycle
HM62W1400H -10 Parameter Read cycle time Address access time Chip select access time Output enable to outpput valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol Min t RC t AA t ACS t OE t OH t CLZ t OLZ t CHZ t OHZ 10 -- -- -- 3 3 0 -- -- Max -- 10 10 5 -- -- -- 5 5 -12 Min 12 -- -- -- 3 3 0 -- -- Max -- 12 12 6 -- -- -- 6 6 -15 Min 15 -- -- -- 3 3 0 -- -- Max -- 15 15 8 -- -- -- 8 8 Unit Notes ns ns ns ns ns ns ns ns ns 1 1 1 1
6
HM62W1400H Series
Write Cycle
HM62W1400H -10 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Output disable to output in high-Z Write enable to output in high-Z Note: Symbol Min t WC t AW t CW t WP t AS t WR t DW t DH t OW t OHZ t WHZ 10 6 6 6 0 0 5 0 3 -- -- Max -- -- -- -- -- -- -- -- -- 5 5 -12 Min 12 8 8 8 0 0 6 0 3 -- -- Max -- -- -- -- -- -- -- -- -- 6 6 -15 Min 15 10 10 10 0 0 8 0 3 -- -- Max -- -- -- -- -- -- -- -- -- 8 8 Unit Notes ns ns ns ns ns ns ns ns ns ns ns 1 1 1 9 8 6 7
1. Transition is measured 200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 2. Address should be valid prior to or coincident with CS transition low. 3. WE and/or CS must be high during address transition time. 4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them. 5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 6. t AS is measured from the latest address transition to the later of CS or WE going low. 7. t WR is measured from the earlier of CS or WE going high to the first address transition. 8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low. A write ends at the earliest transition among CS going high and WE going high. tWP is measured from the beginnig of write to the end of write. 9. t CW is measured from the later of CS going low to the the end of write.
7
HM62W1400H Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
t RC
Address
Valid address t AA t ACS t OH t CHZ
CS t OE OE t OLZ t CLZ Dout High Impedance Valid data t OHZ
Read Timing Waveform (2) (WE = VIH, CS = VIL , OE = VIL )
t RC
Address t OH Dout
Valid address t AA t OH
Valid data
8
HM62W1400H Series
Read Timing Waveform (3) (WE = VIH, CS = VIL , OE = VIL )*2
tRC CS tACS tCLZ Dout High Impedance Valid data High Impedance tCHZ
Write Timing Waveform (1) (WE Controlled)
t WC Address Valid address t AW OE t CW CS*3 t AS WE*3 t OHZ Dout High impedance*5 t DW Din *4 t DH *4 t WP t WR
Valid data
9
HM62W1400H Series
Write Timing Waveform (2) (CS Controlled)
t WC Address Valid address t CW CS *3 t AW t WP WE *3 t AS t WHZ Dout t OW High impedance*5 t DW Din *4 t DH *4 t WR
Valid data
10
HM62W1400H Series
Low VCC Data Retention Characteristics (Ta = 0 to 70C)
This characteristics is guaranteed only for L-version.
Parameter VCC for data retention Symbol VDR Min 2.0 Typ*1 -- Max -- Unit V Test conditions VCC CS VCC - 0.2 V (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V VCC = 3 V, VCC CS VCC - 0.2 V (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V See retention waveform
Data retention current
I CCDR
--
2
300
A
Chip deselect to data retention time Operation recovery time Note:
t CDR tR
0 5
-- --
-- --
ns ms
1. Typical values are at VCC = 3.0 V, Ta = 25C, and not guaranteed.
Low V CC Data Retention Timing Waveform
t CDR V CC 3.0 V V DR 2.2 V CS 0V VCC CS VCC - 0.2 V Data retention mode tR
11
HM62W1400H Series
Package Dimensions
HM62W1400HJP/HLJP Series (CP-32DB)
Unit: mm
32
20.71 21.08 Max
17 10.16 0.13 11.18 0.13
1
3.50 0.26
1.30 Max
0.80 +0.25 -0.17
0.43 0.10 0.41 0.08
1.27
9.40 0.25
0.10
Hitachi Code JEDEC Code EIAJ Code Weight
12
2.85 0.12
CP-32DB MO-061-AB SC-638 1.2 g
0.74
16
HM62W1400H Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
13
HM62W1400H Series
Revision Record
Rev. 0.0 Date Apr. 28, 1997 Contents of Modification Initial issue Drawn by Approved by
14

▲Up To Search▲

Price & Availability of HM62W1400HSERIES

	To Download HM62W1400HSERIES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .